1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) and a fabrication method thereof. More particularly, the present invention relates to a deep trench capacitor and a fabrication method thereof.
2. Description of Related Art
As the device dimension being gradually reduced, the space for accommodating a capacitor of a DRAM device also diminishes. A trench capacitor formed in the substrate can effectively use the space provided by the substrate, and thus is compatible to the demand of the current market. The surface area of above-mentioned trench capacitor can be increased by increasing the depth of the trench. However, as a semiconductor device dimension continues to decrease, the trench dimension of the trench capacitor correspondingly reduces. Accordingly, the aspect ratio of the trench becomes larger and the photolithography process used in forming the deep trench becomes more difficult.
FIG. 1 is a schematic, upper view diagram illustrating an arrangement of a conventional DRAM. FIGS. 2A to 2D are schematic cross-sectional views along the cutting line I–I′ of the diagram in FIG. 1 illustrating a plurality of deep trench capacitors in selected process steps of the fabrication.
Referring concurrently to both FIGS. 1 and 2A, a patterned mask layer 102 is formed on a substrate 100. Using the patterned mask layer 102 as an etching mask, a deep trench 104 is formed in the substrate.
Referring to FIG. 2B, a bottom electrode 106 is formed in the substrate 100 surrounding the bottom of the deep trench 104. A capacitor dielectric layer 108 and a conductive layer 110 are sequentially formed at the bottom of the deep trench. Thereafter, a collar oxide layer 112 is formed on the surfaces of the mask layer 102 and the conductive layer 110 and on the sidewall of the exposed deep trench 104.
Continuing to FIG. 2C, an anisotropic etching is performed to remove the collar oxide layer 112 on the surfaces of the conductive layer 110 and the mask layer 102, leaving only the collar oxide layer 112a on the sidewall of the deep trench 104. A conductive layer 114 is subsequently formed to fill the deep trench 104.
As shown in FIG. 2D, a portion of the conductive layer 114 is removed. Further, the collar oxide layer 112a that is not covered by the conductive layer 114 is also removed. A conductive material then fills the deep trench 104. After removing a portion of the conductive material, a conductive layer 116 is formed.
After the fabrication of the deep trench capacitor is completed, the fabrication of active devices is conducted. Referring to both FIGS. 1 and 2E, an isolation structure 120 is formed in the substrate 100 between two neighboring deep trenches 104 to define the device active regions 118. Thereafter, the patterned mask layer 102 is removed to form the transistors 122 on the surfaces of the isolation structure 120 and the substrate 100.
However, the aforementioned process comprises the following problems.
Due to the increase in density of device integration, the distance between two neighboring deep trenches 104 will be reduced during the fabrication of the deep trench capacitor in order to effectively utilize the area of the wafer. In such a case, a portion of the mask layer 102 between the two neighboring deep trenches 104 will easily be removed during the defining of the deep trenches 104. The substrate 100 underneath the mask layer 102 may also be removed (as indicated by the arrows 124 and 126 in FIG. 2A). In other words, the top film layers (for example, mask layer and the underlying substrate thereof) are etched. For example, portions of the mask layer 102 and the underlying substrate 100 as indicated by the arrow 124 in FIG. 2A are removed, and the depth of the two layers being removed is shallower than the depth 128 of a predetermined shallow trench isolation structure 120. The defect as indicated by the arrow 126 is more a serious issue. The mask layer 102 and a substantial portion of the substrate 100 are removed, wherein the depth of the two layers being removed is greater than the depth 128 of the predetermined shallow trench isolation structure 120.
The defect as indicated by the arrow 126 will affect the subsequent process, leading the formation of an ineffective device. For example, as shown in FIG. 2E, due to the defect as indicated by arrow 126 in FIG. 2A, the two neighboring deep trenches 104 can not be completely isolated (as indicated by arrow 130) even after the formation of the isolation structure 120. As a result, the conductive layers 114 in the neighboring deep trenches 104 are electrically connected to create a short in the device. Further, the operation of the capacitor may also be affected. The aforementioned problems are more prominent in the processing of small dimension devices.